Verilator
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Hello! Does anyone there work with VHDL? Verilog especificly? I'm trying to translate some codes from Verilog to C++! :) I need some help! :(( Regards :-D
VHDL is for hardware implementation and C++ is for software implementation. They are not equivalent so please be more specific about what you are trying to do. Elaine :rose:
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VHDL is for hardware implementation and C++ is for software implementation. They are not equivalent so please be more specific about what you are trying to do. Elaine :rose:
Hi! Thanks for the reply. Actually I'm trying to make a simulation. With the current Verilog tool that I have, I can simulate, but it takes too long to simulate! In c++ it can be maybe 10x faster or 20x. The problem is... corventing the whole code into C++. I'm getting so many troubles! I really have no clue, I have fixed all the Verilator warnings, but the errors seem endless. hehehe but I cant give up, not yet :P Regards!
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Hi! Thanks for the reply. Actually I'm trying to make a simulation. With the current Verilog tool that I have, I can simulate, but it takes too long to simulate! In c++ it can be maybe 10x faster or 20x. The problem is... corventing the whole code into C++. I'm getting so many troubles! I really have no clue, I have fixed all the Verilator warnings, but the errors seem endless. hehehe but I cant give up, not yet :P Regards!