Need help with internal timing constraint in FPGAs
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I'm currently trying to implement an IP-Core on a Cyclone V 5CSEBA6U23I7 FPGA-HPS System using Altera Quartus II and TimeQuest Analyzer. The Verilog code pasted below produces a timing problem, namely the assignment
fifo_wdata_289[255:0] <= {fifo_out,fifo_wdata_289[255:16]};, which writes the output of one FIFO into another FIFO register array. The FIFOs in use are asynchronous, but the signals used are on the same clock domain. This is being placed on the chip with a clock skew of -2.255 ns, which is a little bit less than a whole period (288 MHz clock => 3.47 ns), and makes TimeQuest complain, that the constraints are being violated. The recommendation of TimeQuest is to Reduce the levels of combinational logic for the path (Issue Long Combinational Path) with Extra levels of combinational logic = 1, which you could get a perfect reference here [^]Discussion on the influencing factors of clock in FPGA design[^]. The 288 MHz clock is generated via PLL and I'm using Timeconstraint files (sdc) with commands derive_pll_clocks and derive_clock_uncertainty. My question now is how to solve this problem, since I only have one layer of combinational logic (Demuxer and routing, as suggested by the assignment) and thus have no idea how to reduce that. Is there any other way I can make sure the timing requirement is met, or is there a better way to program this statemachine?case(stateProc) 2'b00: begin if(~fifo_empty&~fifo_full_289) begin fifo_wdata_289[255:0] <= {fifo_out,fifo_wdata_289[255:16]}; fifo_wdata_289[287:256] <= {2'b11,fifo_wdata_289[287:258]}; if(imgSize >= maxImgSize - 32'd2)//image done, transmit data and fire irq begin fifo_wdata_289[288] <= 1; stateProc <= 2'b01; imgSize <= 32'd0; end else if(fifo_wdata_289[258])//process transfer without irq //258 high means that 256 has been written in this cycle and 258 in the previous cycle begin fifo_wdata_289[288] <= 0; stateProc <= 2'b01;