Memory
-
I’m trying to get a better understanding of how RAM memory works. I brought up this question before. This time I’m trying to find out a little bit more. There is no optical fiber on the motherboard hence in the scenario where you want to place 32 bits in memory if you want to send them at one time you need 32 copper lines connecting the CPU socket to the memory slots. What happens if you want to send more information. Let’s say you want to send four 32 bit integers. Before sending the actual data does the CPU ( the Operating System) use the same 32 lines to instruct the memory slots where should the integers about to be sent be placed? How does the memory know the address range in which it should place the four integers?
-
I’m trying to get a better understanding of how RAM memory works. I brought up this question before. This time I’m trying to find out a little bit more. There is no optical fiber on the motherboard hence in the scenario where you want to place 32 bits in memory if you want to send them at one time you need 32 copper lines connecting the CPU socket to the memory slots. What happens if you want to send more information. Let’s say you want to send four 32 bit integers. Before sending the actual data does the CPU ( the Operating System) use the same 32 lines to instruct the memory slots where should the integers about to be sent be placed? How does the memory know the address range in which it should place the four integers?
CPU sockets of today has a tremendous number of 'pins' (they aren't really pins nowadays, but the name sticks), typically 1200-1500. Usually, far more than 32 of these carry data to/from RAM. More typical is 128 or 256, the length of a cache line. If you want to modify anything less (such as a single byte or a 32 bit word), the CPU must fetch the entire cache line from RAM, modify the part of it that you want to modify, and write the entire cache line back to memory. The CPU uses another set of pins to indicate the RAM address to be read from or written to. Since the arrival of 32 bit CPUs, the CPU has rarely been built to handle as much RAM as the logical address space; the 386 did not have 32 address lines, you could not build a 386 PC with 4 GB memory. Nor does today's 64 bit CPUs have 64 address lines. The memory management system will map ("condense", if you like) the used memory pages spread over the entire 64 bit address space, even multiple 64 bit spaces - one for each process, down to the number of address pins required to cover the amount of physical RAM that you have got. Note that when transfers between RAM and the CPU cache (inside the CPU chip) goes in units of an entire cache line of, say, 128 bits or 16 bytes, there is no need to tell the RAM which of the 16 byte(s) are actually used - they are transferred anyway. So there is no need to spend address lines for the lowermost 4 bits of byte address. The number of external pins is a significant cost factor in the production of a chip, so saving 4 bits gives an economic advantage. In the old days, pins were even costlier, and you could see CPUs that first sent the memory address out on a set of pins during the first clock cycle. The memory circuits latched this address, for use in the next clock cycle, when the CPU transferred the data value to be written on the same pins as those used for the address. Or reading: In the first cycle, the CPU presents the address it wants to read; in the next cycle, the RAM returns the data on the combined address/data lines. There were even designs where the address was too long to be transferred in a single piece: In cycle 1, the high address were transferred, in cycle 2 the low address, and in cycle 3, data was transferred. (And in those days, you fetched/wrote a single byte at a time, and cache was rarely seen.) This obviously put a cap on the machine speed, when you could retrieve/save another data byte no faster than one every two or three clock cycles. To win the speed race, general proce
-
CPU sockets of today has a tremendous number of 'pins' (they aren't really pins nowadays, but the name sticks), typically 1200-1500. Usually, far more than 32 of these carry data to/from RAM. More typical is 128 or 256, the length of a cache line. If you want to modify anything less (such as a single byte or a 32 bit word), the CPU must fetch the entire cache line from RAM, modify the part of it that you want to modify, and write the entire cache line back to memory. The CPU uses another set of pins to indicate the RAM address to be read from or written to. Since the arrival of 32 bit CPUs, the CPU has rarely been built to handle as much RAM as the logical address space; the 386 did not have 32 address lines, you could not build a 386 PC with 4 GB memory. Nor does today's 64 bit CPUs have 64 address lines. The memory management system will map ("condense", if you like) the used memory pages spread over the entire 64 bit address space, even multiple 64 bit spaces - one for each process, down to the number of address pins required to cover the amount of physical RAM that you have got. Note that when transfers between RAM and the CPU cache (inside the CPU chip) goes in units of an entire cache line of, say, 128 bits or 16 bytes, there is no need to tell the RAM which of the 16 byte(s) are actually used - they are transferred anyway. So there is no need to spend address lines for the lowermost 4 bits of byte address. The number of external pins is a significant cost factor in the production of a chip, so saving 4 bits gives an economic advantage. In the old days, pins were even costlier, and you could see CPUs that first sent the memory address out on a set of pins during the first clock cycle. The memory circuits latched this address, for use in the next clock cycle, when the CPU transferred the data value to be written on the same pins as those used for the address. Or reading: In the first cycle, the CPU presents the address it wants to read; in the next cycle, the RAM returns the data on the combined address/data lines. There were even designs where the address was too long to be transferred in a single piece: In cycle 1, the high address were transferred, in cycle 2 the low address, and in cycle 3, data was transferred. (And in those days, you fetched/wrote a single byte at a time, and cache was rarely seen.) This obviously put a cap on the machine speed, when you could retrieve/save another data byte no faster than one every two or three clock cycles. To win the speed race, general proce
I get the picture, thank you