It's more about structure of caches and the speed of buses between them. I believe in Intel's design, two cores share a single L2 cache (of 4MB I think in current Xeons but I think I've also seen 6MB). A 'Core 2 Quad'/Xeon 53xx basically just has two Core 2 Duo/Xeon 51xx chips wired together in the same package. The interconnections between the two chips are wired to the same Front Side Bus that goes off-package to the memory controller. When fetching data that isn't already in its own cache the core (pair) basically just broadcasts 'please give me the data at address XXX' and the other core might respond from its cache if present, but that blocks the second core from fetching from main memory. It's a larger problem with systems with multiple sockets connected to the same bus because traffic between cores on the same package ends up on the FSB rather than being completely private, and can therefore block memory requests from a different package. By contrast the AMD 'Barcelona's have an on-chip memory controller and all four cores share a single large cache. Theoretically this should lead to less inter-core blocking. A multi-socket AMD system is a Non-Uniform Memory Access system - each socket has different RAM sockets connected to it, and if you want data from memory that's connected to a different processor package, you have to ask the other package for that data (which may also respond from cache rather than main memory). Windows Server 2003 understands NUMA systems and will try to allocate memory for threads from the appropriate areas of physical memory. So, if the bottleneck in performance on your system was the bandwidth to main memory, the AMD solution would probably be better. On most systems, though, it's disk bandwidth. Further, in a lot of software, the locality of reference is commonly good enough to keep all the data that a thread is referencing in the caches, so the FSB isn't used as much as you might think (also the FSB is a bit faster than the actual memory buses now, so the FSB won't be saturated even if main memory is, I think). The terminology is getting very difficult for multi-core systems, especially where HyperThreading is also involved. 'Chip' isn't too good when you have multiple actual chips in the same package.
Stability. What an interesting concept. -- Chris Maunder
